Vulkan Compute for Diffusion Under 33ms on Snapdragon

Meta description: Bypass NNAPI scheduling overhead and drive a quantized INT8 diffusion model through Vulkan compute on Snapdragon 8 Gen 3, staying under 33ms per frame.

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TL;DR

NNAPI’s dispatcher adds measurable scheduling latency that blows your frame budget on inference-heavy pipelines. Driving a quantized INT8 diffusion model directly through Vulkan compute shaders — with precise memory barrier placement, pre-allocated descriptor set pools, and a tile-based execution strategy — gets you to real-time texture synthesis under 33ms on modern Snapdragon silicon.

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The problem with NNAPI on a tight frame budget

NNAPI is easy to treat as a black box. Plug it in, it handles hardware negotiation, and then you’re spending an afternoon debugging inconsistent latency under load with no obvious culprit.

That inconsistency is baked into the design. NNAPI was built for broad hardware compatibility, not deterministic scheduling. Its internal dispatcher negotiates between DSP, NPU, and GPU backends at runtime. On Snapdragon 8 Gen 3, that negotiation introduces overhead that compounds badly when you’re running tile-based inference in a render loop. You don’t need flexibility — you need control.

The fix: bypass NNAPI entirely and drive your quantized model through Vulkan compute pipelines you own. This isn’t theoretical. It’s the approach that closes the gap between a sluggish 45ms inference pass and one that fits inside a 33ms frame.

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Quantization toolchain: establishing the baseline

Before the pipeline design matters, your model needs to be INT8-quantized and verified on-device. Three toolchains cover most production cases:

• ONNX Runtime with QAT (Quantization-Aware Training): the most reproducible path if you control the training loop. Export to ORT format and target the QNN or XNNPACK execution provider.
• TFLite post-training quantization: lower friction for existing TensorFlow models. Full-integer quantization (tf.lite.Optimize.DEFAULT) with a representative dataset produces models that run reliably on Adreno via GPU delegate.
• Custom GLSL INT8 kernels via Vulkan compute: the approach in this post — most control, highest integration cost. You own the quantization scheme (symmetric per-channel is the practical default) and write shader-level dequantization inline.

The benchmarks below assume the third path: GLSL compute shaders with symmetric INT8 weights dequantized to FP16 for accumulation. If you’re adapting this to TFLite or ORT, the barrier and descriptor set patterns apply equally; only the dispatch layer differs.

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Architecture overview: the tile pipeline

The target model is a quantized INT8 stable diffusion tile generator — a stripped-down UNet that operates on 64×64 or 128×128 tiles rather than full-resolution latent space. Each tile is an independent dispatch job on the GPU, which means you can pipeline tile inference against framebuffer composition with careful synchronization.

Execution path:

[ CPU: Tile Scheduler ]
        |
        v  VkCommandBuffer submission
[ Compute Shader: INT8 UNet Forward Pass ]
        |
        v  VkImageMemoryBarrier (COMPUTE_SHADER -> TRANSFER)
[ Transfer: Tile Blit to Texture Atlas ]
        |
        v  VkImageMemoryBarrier (TRANSFER -> FRAGMENT_SHADER)
[ Fragment Shader: Final Composite ]

Barrier placement between compute and transfer is the single biggest lever you have on stall time.

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Memory barriers: where latency gets left on the table

Vulkan gives you explicit synchronization, and that’s both its power and its footgun. A VkImageMemoryBarrier that’s too coarse — using VK_PIPELINE_STAGE_ALL_COMMANDS_BIT as your source stage — will serialize the entire GPU pipeline unnecessarily.

For the inference-to-blit transition, the correct barrier is:

VkImageMemoryBarrier barrier{};
barrier.srcAccessMask  = VK_ACCESS_SHADER_WRITE_BIT;
barrier.dstAccessMask  = VK_ACCESS_TRANSFER_READ_BIT;
barrier.oldLayout      = VK_IMAGE_LAYOUT_GENERAL;
barrier.newLayout      = VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL;

vkCmdPipelineBarrier(
    cmd,
    VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT,  // srcStageMask
    VK_PIPELINE_STAGE_TRANSFER_BIT,         // dstStageMask
    0, 0, nullptr, 0, nullptr, 1, &barrier
);

Scoping your source and destination stages precisely means the GPU’s fixed-function hardware — texture units, rasterizer — keeps running while the barrier resolves only what needs to resolve.

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Descriptor set pooling: eliminate allocation stalls

Dynamic descriptor set allocation mid-frame is a silent killer. Every vkAllocateDescriptorSets call against an insufficiently sized pool can trigger a driver-side reallocation.

Pre-allocate at pipeline initialization time with a multiplier that accounts for your tile count:

VkDescriptorPoolCreateInfo poolInfo{};
poolInfo.maxSets       = MAX_TILES_IN_FLIGHT * FRAMES_IN_FLIGHT;
poolInfo.poolSizeCount = static_cast<uint32_t>(poolSizes.size());
poolInfo.pPoolSizes    = poolSizes.data();

Pair this with VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT only if you need per-tile recycling. For a fixed tile grid, skip the flag — the simpler reset path is faster.

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Benchmark: Vulkan direct vs. NNAPI dispatch

Metric	NNAPI (GPU backend)	Vulkan Direct	Delta
Mean tile inference	~28ms	~18ms	−10ms
99th percentile	~52ms	~26ms	−26ms
Scheduler jitter	High	Minimal	Significant
Frame budget headroom	None	~7ms	Available
Driver negotiation overhead	Present	None	Eliminated

The 99th percentile gap is where NNAPI actually hurts. That 26ms improvement isn’t a rounding error — it’s the difference between a render loop that feels responsive and one that visibly stutters. Mean latency alone won’t tell you whether your pipeline is viable. A pipeline averaging 28ms that spikes to 52ms on every tenth frame isn’t acceptable, regardless of the mean.

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The 33ms budget: how the tile pipeline stays inside it

With Snapdragon 8 Gen 3’s Adreno 750, a 128×128 INT8 tile inference pass through a quantized UNet fits comfortably inside 18–22ms in isolation. The remaining budget covers:

• Command buffer recording and submission: ~2ms
• Barrier resolution and blit: ~3ms
• Final composite fragment pass: ~4ms
• Headroom for driver variance: ~4ms

Running two tiles in flight with double-buffered descriptor sets lets you overlap the transfer of tile N with compute for tile N+1, effectively hiding blit latency behind inference latency.

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Takeaways

1. Cut NNAPI out of your hot path. If you own the target GPU (Adreno, Mali, or Immortalis) and your model is quantized, Vulkan compute gives you deterministic scheduling that NNAPI can’t match. The latency recovery alone justifies the integration effort.

2. Scope your pipeline barriers precisely. Replace any VK_PIPELINE_STAGE_ALL_COMMANDS_BIT usage in your inference pipeline with the narrowest applicable stage flags. This single change can recover several milliseconds at the 99th percentile.

3. Pre-allocate descriptor sets at pipeline init. Size your descriptor pool to tile_count × frames_in_flight at startup. Mid-frame allocation is the first thing to eliminate in a stable render loop.

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